1. Field of the Invention
The invention relates in general to a memory and a driving method therefor, and more particularly to a semi-conductor memory and a driving method therefor.
2. Description of the Related Art
Every electronic product needs a memory for the purposes of data storage or operation buffer. Conventional semi-conductor memory includes a number of memory cells arranged in matrix form. Each memory cell is enabled by a corresponding word line. Each memory cell can be formed by a transistor for instance. When the memory is read or programmed or erased, corresponding bit line and word line of the memory cell to be operated are enabled accordingly. Whether the bit line is electrically connected to a sensing amplifier or a ground is determined according to a select switch.
A larger capacity of the memory is demanded. Particularly for the large capacity semi-conductor memory manufactured especially according to the non-BD (buried diffusion) strapping process or having a longer bit line memory, the source side body effect increases and the drain side voltage drops as the capacity of memory increases. Consequently, when two voltages of the same magnitude are respectively inputted to read two memory cells storing the same data but are positioned at different word lines, the currents obtained could differ widely.
For example, when two voltages of 5 V are provided to read two memory cells storing data 0 but are respectively positioned at the 1st word line and the 128th word line, the current flowing through the memory cell positioned at the 1st word line equals 6 uA, and the current flowing through the memory cell positioned at the 128th word line equals 12 uA. As the current of the memory cell differs wider, the range of the current distribution is also broaden, which making the circuit design even complicated.
Besides, when the memory cell is programmed, the efficiency of programming is reduced because of the following factors: (1) the cell drain side has voltage drop due to the buried diffusion voltage drop (BD voltage drop) or the metal bit line voltage drop (MBL voltage drop); (2) the cell source side has voltage increase due to the buried diffusion voltage increase (BD voltage increase) or the metal bit line voltage increase (MBL voltage increase). The decrease in the efficiency of programming is most significant when larger program current is used. Therefore, how to provide a method to narrow the range of the current distribution, reduce the complication of circuit design and increase the efficiency of programming is essential to the memory having the buried diffusion resistance loading (BD resistance loading) or the metal bit line resistance loading (MBL resistance loading).